As modern processor speeds have increased over time, the use of on-chip static random access memory (SRAM) has become more common. An advantage of SRAM memories is that they do not require refresh cycles to retain data. Dynamic random access memories (DRAMs) do require refresh operations which can result in adverse power consequences which are not suffered when using SRAM technology. However, a problem exists with all types of SRAMs in that perfect data retention potential has not been realized due to soft error rate phenomenon. In other words, open circuit defects, dubbed soft defects, are capable of causing retention failures and can be undetectable using conventional retention detection techniques.
In order to address this issue, a set of open circuit tests and memory current tests, termed as soft defect detection testing (SDDT), has been developed. One test in this set of tests is known as an array current test (ACT). During the array current test, the amount of current being drawn by a given memory block or memory array is measured by an on-board current detect circuit in the prior art. Since the amount of current used by a memory cell which contains a soft defect is greater than those which are non-defective, it can be determined whether or not a soft defect is present through a current measurement.
A problem exists with prior art array current tests as used on microcontrollers or processors, in that the on-board current detection circuit often requires multiple design passes and mask changes in order to determine the actual current range in which to operate. This is because for new integrated circuit designs the precise current level of a memory array is not known until devices are manufactured onto silicon wafers. Therefore, on the first set of manufactured wafers, the current detection circuitry is usually manufactured to specifications which do not allow for proper memory array current measurement. Due to this first improper design, significant redesign of the on-board current detection devices are needed to obtain proper SDDT testing. Therefore, the need exists for an array current test which eliminates the necessity for making multiple mask versions of a design in order to obtain proper current measurements for SDDT testing.